The present application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-363370 filed on Oct. 23, 2003, with the Japanese Patent Office, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a ferroelectric memory in which the latch timing of a sense amplifier is adjusted.
2. Description of the Related Art
A ferroelectric memory (FRAM, FeRAM) is used as a memory medium for an IC card or the like due to the use of a ferroelectric capacity as a memory cell that achieves the retention of data during power-off periods.
FIG. 1 is a drawing showing an example of the construction of a related-art ferroelectric memory. The circuit shown in FIG. 1 is a portion relevant to the reading of a ferroelectric memory, and includes 2T2C-type (2-transistor-and-2-capacitor-type) memory cell 1, a pre-sense amplifier 2, a pre-sense amplifier 3, a Vth generating circuit 4, a minus voltage generating circuit 5, and a sense amplifier 6.
In actual construction, a plurality of memory cells 1 is arranged in a matrix form. For the sake of simplicity of illustration, however, only one cell is shown in FIG. 1. In the memory cell 1, a word line WL, a plate line PL, bit lines BL and BLX, access transistors N1 and N2, and ferroelectric capacitors F1 and F2 are provided.
In the ferroelectric memory, a write operation is performed by applying a positive or negative voltage to the ferroelectric capacitors for polarization, and a read operation is performed by detecting the presence/absence of a reversed polarization current when a positive voltage is applied to the ferroelectric capacitors. In the write operation, the word line WL is placed in a selected state (HIGH), thereby turning on the access transistor N1. When a positive or negative voltage is applied between the bit line BL and the plate line PL, this voltage is applied to the ferroelectric capacitor F1, resulting in desired data being stored. When writing xe2x80x9c0xe2x80x9d data, the bit line BL is set to 0 V, and the plate line PL is set to a power supply voltage VDD. When writing xe2x80x9c1xe2x80x9d data, the bit line BL is set to the power supply voltage VDD, and the plate line PL is set to 0 V. By following the same procedure, the ferroelectric capacitor F1 stores data that is inverse to the data stored in the ferroelectric capacitor F2. Since the polarization of the ferroelectric capacitors is retained even after the applied voltage is removed following the write operation, the stored data remains as nonvolatile data.
In a read operation, the word line WL is selectively activated to turn on the access transistor N1, and the plate line PL is set to the power supply voltage VDD. The bit line BL is maintained substantially at a ground potential GND by the pre-sense amplifier 2, and a positive voltage is applied to the ferroelectric capacitor F1. When xe2x80x9c0xe2x80x9d is stored in the ferroelectric capacitor F1, the voltage applied to the ferroelectric capacitor F1 has the same polarity as used in the write operation, thereby resulting in no reversal of polarization. In this case, comparatively small electric charge flows into the bit line BL. When xe2x80x9c1xe2x80x9d is stored in the ferroelectric capacitor F1, the voltage applied to the ferroelectric capacitor F1 has a reversed polarity compared with the polarity used in the write operation, thereby resulting in the reversal of polarization. In this case, comparatively large electric charge flows into the bit line BL. The pre-sense amplifier 2 detects this current, and converts it into a voltage signal. By the same token, the pre-sense amplifier 3 detects a current from the ferroelectric capacitor F2, and converts it into a voltage signal. The sense amplifier 6 amplifies a difference of the output potentials of the pre-sense amplifiers 2 and 3 up to the level of the power supply voltages VDD and GND.
The pre-sense amplifier 2 includes switches S1 and S3, a Pch-MOS transistor P1, and capacitors C1 and C3. The pre-sense amplifier 3 includes switches S2 and S4, a Pch-MOS transistor P2, and capacitors C2 and C4. The sense amplifier 6 includes Pch-MOS transistors P3-P7, Nch-MOS transistors N3-N7, switches S5 and S6, and an inverter I1.
FIG. 2 is a diagram showing signal waveforms for explaining the operation of the related-art circuit of FIG. 1. In the following, a description will be given of the operation of the circuit of FIG. 1 with reference to FIG. 2.
Data xe2x80x9c1xe2x80x9d is stored in the ferroelectric capacitor F1, and data xe2x80x9c0xe2x80x9d is stored in the ferroelectric capacitor F2. In FIG. 2, the switches S1 and 52 are ON (i.e., closed) up to timing T1, so that the bit lines BL and BLX are fixed to the ground potential GND. After timing T1, the switches S1 and S2 are OFF (i.e., open), so that the bit lines BL and BLX are released. The Vth generating circuit 4 generates a potential that is equal to Vth (MOS threshold value) when the sources (i.e., the bit lines BL and BLX) of the Pch-MOS transistors P1 and P2 are at the ground potential GND. This potential is lower than GND.
The minus voltage generating circuit 5 generates a negative potential VMINUS. The negative potential VMINUS is xe2x88x923 V, for example. The switches S3 and S4 are ON until timing T1, thereby setting the drains (i.e., nodes MINUS and MINUSX) of the Pch-MOS transistors P1 and P2 to the negative potential VMINUS. After timing T1, the switches S3 and S4 are OFF, so that the nodes MINUS and MINUSX are released. From timing T1 to timing T2, the potential of the nodes MINUS and MINUSX is maintained at the negative potential VMINUS by means of the capacitors C1 and C2.
At timing T2, the word line WL and the plate line PL are changed to VDD (e.g., 3 V). The access transistors N1 and N2 are turned on, and a positive voltage is applied to the ferroelectric capacitors F1 and F2. Since the ferroelectric capacitor F1 with stored data xe2x80x9c1xe2x80x9d receives a voltage having an opposite polarity compared with the polarity used in the write operation, a large amount of reversed electric charge flows into the bit line BL due to the reversal of polarization. In response, the potential of the bit line BL tries to rise. Since Vth is being applied to the gate of the Pch-MOS transistor P1, even a slight increase in the potential of the bit line BL causes the Pch-MOS transistor P1 to turn on. Because of this, electric charge equal to the reversed electric charge flows from the bit line BL to the node MINUS, maintaining the potential of the bit line BL close to GND. In response to the influx of reversed electric charge, the potential of the node MINUS that was held steady by the capacitor C1 rises significantly, as shown in FIG. 2.
The voltage applied to the ferroelectric capacitor F2 with stored data xe2x80x9c0xe2x80x9d, on the other hand, has the same polarity as used in write operation, resulting in no reversal of polarization. In this case, comparatively small electric charge flows into the bit line BLX. In response, the potential of the bit line BLX tries to rise. Since Vth is being applied to the gate of the Pch-MOS transistor P2, even a slight increase in the potential of the bit line BLX causes the Pch-MOS transistor P2 to turn on. Because of this, electric charge flows from the bit line BLX to the node MINUSX, maintaining the potential of the bit line BLX close to GND. With the inflow of electric charge, the potential of the node MINUSX that was held steady by the capacitor C2 rises as shown in FIG. 2. Since the stored data is xe2x80x9c0xe2x80x9d, the rise of the potential of the node MINUSX is smaller than the rise of the potential of the node MINUS.
The switches S5 and S6 of the sense amplifier 6 are ON until timing T1, so that respective terminals OUT and OUTX of the capacitors C3 and C4 are fixed to GND until timing T1. The opposite ends MINUS and MINUSX of the capacitors C3 and C4 are fixed to the negative potential VMINUS until the timing T1, as previously described. After timing T1, the switches S5 and S6 are OFF, so that the nodes OUT and OUTX are released. Since the capacitors C3 and C4 keep the potential difference between their respective opposite ends, the potentials of the nodes OUT and OUTX change in the same manner as the potential changes of the nodes MINUS and MINUSX, respectively. Thus, the potential waveforms of the nodes OUT and OUTX are the same as the potential waveforms of the nodes MINUS and MINUSX, respectively, with an upward potential shift by |VMINUS|, which results in positive potentials being obtained with the ground potential GND serving as a reference.
The sense amplifier 6 is a latch-type sense amplifier, which latches the nodes OUT and OUTX as its inputs, and amplifies the inputs to VDD and GND. The MOS transistors P4, P5, N4, and N5 together make up two inverters that are cross-coupled to each other. The MOS transistors P3 and N3 serve as switches for disconnecting these two inverters from a power supply. The MOS transistors P6, N6, P7, and N7 are transfer gates. Up to timing T3, a latch drive signal SAPOWER is LOW, so that the two inverters cross-coupled to each other are disconnected from the power supply, being placed in a floating state. The transfer gates are ON, so that the nodes OUT and OUTX are respectively coupled to nodes SAOUT and SAOUTX situated at the cross-coupling points. When the latch drive signal SAPOWER changes to HIGH at timing T3, the transfer gates become nonconductive, and the two cross-coupled inverters are turned on. In response, the potentials of the nodes SAOUT and SAOUTX are amplified to a full range between VDD and GND. These amplified signals are provided as read outputs.
It should be noted that switching operations and amplification operations in a read operation are the same as those described above even if data xe2x80x9c0xe2x80x9d is stored in the ferroelectric capacitor F1 and data xe2x80x9c1xe2x80x9d is stored in the ferroelectric capacitor F2 in an opposite manner to the above example.
[Patent Document 1] Japanese Patent Application Publication No. 2002-133857
[Non-Patent Document 1] xe2x80x9cPassport of Internet Age, FRAM Smart Card,xe2x80x9d 2003, FUJITSU, LTD.,  less than URL:http://edevice.fujitsu.com/fj/CATALOG/AD05/05-00023/index_j.html greater than 
[Non-Patent Document 2] Shoichiro Kawashima, et. al., IEEE Journal of Solid-State Circuits, May, 2002, Vol. 37, No. 5, pp. 592-598
FIG. 3 is an expanded view of the waveforms of the nodes OUT and OUTX and the latch drive signal SAPOWER shown in FIG. 2. In FIG. 3, the potentials of the nodes OUT and OUTX rise in response to the reading of a memory cell, providing a potential difference xcex94V at timing T3 when the sense amplifier 6 starts an operation. The sense amplifier 6 amplifies this potential difference that is received as an input. In general, the characteristics of ferroelectric have large manufacturing variation, and temperature and power supply dependency is also strong. Moreover, the waveform of the potential of the nodes OUT and OUTX is also affected by relative variation between the capacitors F1 and F2 of the memory cell and the capacitors C1 and C2.
If the capacitors F1 and F2 of the memory cell are larger than design specs due to manufacturing variation or temperature and power supply dependency, the potential of the nodes OUT and OUTX may excessively rise as shown in FIG. 4. In this case, the potential of the node OUT corresponding to the reading of data xe2x80x9c1xe2x80x9d exceeds VDD (e.g., 3 V) to saturate approximately at VDD+0.6 V. This is because, with the back gate of the Pch-MOS transistor P1 in the pre-sense amplifier 2 being connected to GND, the PN junction between the sauce/drain and the back gate becomes a forward direction in response to the potential of the source/drain trying to exceed about +0.6 V, which results in the flow of a current that prevents the potential of the source/drain from rising. That is, the potential of the node MINUS does not exceed a certain point that is approximately at +0.6 V, and the potential of the node OUT does not rise above a certain point that is approximately at VDD+0.6 V.
On the other hand, the potential of the node OUTX corresponding to the reading of data xe2x80x9c0xe2x80x9d continues to rise with time because there is still some distance to go before reaching the saturation point.
If timing T3 is positioned as illustrated in FIG. 4, only a relatively small potential difference xcex94V is obtained at the latch timing T3 whereas a sufficiently large potential difference xcex94Vxe2x80x2 is produced at timing earlier than the latch timing T3. In this case, the sense amplifier 6 may sense data incorrectly due to the small potential difference that it receives. Moreover, the sense amplifier 6 is a latch-type sense amplifier, so that its gain is largest around VDD/2. When both of the two inputs are close to VDD as shown in FIG. 4, the gain is small, resulting in an increase of the possibility of incorrect sensing.
Accordingly, there is a need for a semiconductor memory device in which the latch timing is adjusted in response to manufacturing variation and/or temperature and power supply dependency of ferroelectric, thereby providing for a latch operation to be performed with respect to a sufficiently large potential difference at a position that is not close to VDD.
It is a general object of the present invention to provide a semiconductor memory device that substantially obviates one or more problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be presented in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a semiconductor memory device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages in accordance with the purpose of the invention, the invention provides a semiconductor memory device, including a memory cell, a signal line on which a potential responsive to data read from the memory cell appears, a potential detecting circuit which outputs a detection signal in response to detecting that the potential on the signal line exceeds a predetermined potential, and a sense amplifier which starts amplifying the potential on the signal line in response to the detection signal.
In the semiconductor memory device described above, the potential detecting circuit detects that the potential responsive to the read data exceeds the predetermined potential, and the sense amplifier amplifies the data (i.e., performs a latch operation) at timing responsive to such a detection. Accordingly, the latch operation is performed at earlier timing where a rise of the data potential is excessively rapid, performed at standard timing where a rise of the data potential is standard, and performed at later timing where a rise of the data potential is excessively slow. With this provision, the latch timing is adjusted according to manufacturing variation and/or temperature and power supply dependency of ferroelectric, thereby achieving accurate data sensing by latching sense amplifier inputs having a sufficiently large potential difference at a position that is not close to VDD.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.